1. Field of the Invention
This invention relates generally to a class of non-volactile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates to methods and means to erase digital data from a flash EEPROM cell and for eliminating trapped charges from the flash EEPROM cell to prevent closure of the difference of the programmed threshold voltage and the erase threshold voltage of the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM FIG. 1 illustrates a cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell 10 is formed within a P-type substrate 12. An N-type material is implanted within the P-type substrate 12 to a lightly doped concentration to for the N-well 47. Within the N-well 47, a P-type material is implanted to a lightly doped concentration to form the P-well 45. An N.sup.+ drain region 14 and an N.sup.+ source region 16 are formed within the P-type well 45.
A relatively thin gate dielectric 36 is deposited on the surface of the P-type substrate 12. The thin gate dielectric 36 will also be referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate 32 is formed on the surface of the gate dielectric 36 above the channel region 34 between the drain region 14 and source region 16. An interpoly dielectric layer 30 is placed on the floating gate 32 to separate the floating gate 32 from a second layer of poly-crystalline silicon that forms a control gate 28.
A P+ diffusion 18 is placed in the P-type substrate 12 to provide a low resistance path from a terminal 20 to the P-type substrate. The terminal 20 will be attached to a substrate voltage generator VSub. In most application of an EEPROM, the substrate voltage generator VSub will be set to the ground reference potential (0V).
The source region 16 will be connected to a source voltage generator VS through the terminal 22. The control gate 28 will be connected through the terminal 26 to the control gate voltage generator VG. And the drain region 14 will be connected through the terminal 24 to the drain voltage generator VD. The P-well 45 is connected to a P-well voltage generator VPw through terminal 44. The N-well 47 is connected to the N-well voltage generator VNw through the terminal 46.
According to conventional operation, the flash EEPROM cell 10 is programmed by setting the gate control voltage generator VG to a relatively high positive voltage (on the order of 10V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS and the P-well voltage generator VPw are set to the ground reference potential (0V). The N-well voltage generator VNw is disconnected from the terminal 46 to allow the N-well 47 to float.
With the voltages as described above, hot electrons will be produced in the channel 34 near the drain region 14. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 36 and trapped on the floating gate 32. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process, some of the hot electrons will be trapped 42 in the tunneling oxide 36 or in surface states 40 at the surface of the P-type substrate 12. These trapped electrons will cause the threshold voltage of the erased flash EEPROM cell 10 to increase.
U.S. Pat. No. 5,481,494 (Tang et al. 494), U.S. Pat. No. 5,485,423 (Tang et al. 423), U.S. Pat. No. 5,412,608 Oyama), U.S. Pat. No. 5,414,669 (Tedrow et al.), U.S. Pat. No. 5,790,460 (Chen et al.), U.S. Pat. No. 5,416,738 (Shrivasta), U.S. Pat. No. 5,546,340 (Hu et al.), and U.S. Pat. No. 5,781,477 (Rinerson et al.) each describe a form of erasing a flash EEPROM conventionally referred to as Negative Gate Erase. To erase the flash EEPROM cell 10 using Negative Gate Erase, as shown in FIG. 2, a moderately high positive voltage (on the order of 5V) is generated by the source voltage generator VS. Concurrently, the gate control voltage generator VG is set to a relatively large negative voltage (on the order of -10V). The substrate voltage generator VSub and the P-well voltage generator VPw are set to the ground reference potential. The drain voltage generator VD and the N-well voltage generator VNw are respectively usually disconnected from the terminal 24 to allow the drain region 14 to float from the terminal 44 to allow the N-well 47 to float. Under these conditions there is a large electric field developed across the tunneling oxide 36 in the source region 16. This field causes the electrons trapped in the floating gate 32 to flow to portion of the floating gate 32 that overlaps the source region 16. The electrons are then extracted to the source region 16 by the Fowler-Nordheim tunneling.
Referring back to FIG. 1, during the erasure process, because of band to band tunneling, some positive charges or "hot holes" 38 are forced into the tunneling oxide 36 and trapped there in the tunneling oxide 36. Further, defects 40 at the interface of the tunneling oxide 36 and the P-well 45 will create trapped positive charges. These trapped positive charges or "hot holes" 38 and the interface traps 40 will cause the threshold voltage of the programmed flash EEPROM cell 10 to decrease. As can be shown in FIG. 3, after repeatedly performing write/erase cycling, the combination of the decrease 52 in the programmed threshold voltage 50 and the increase 57 in the erased threshold voltage 55 will cause the separation of the programmed threshold voltage 50 and the erased threshold voltage 55 to close until the flash EEPROM cell 10 fails. At this time, the flash EEPROM will operate less reliably to store digital data.
Further Tang et al. 494 shows a method for tightening the threshold voltage V.sub.T distribution of an array of flash EEPROM cells. The moderately high positive voltage (5V) that is applied to the source regions of the array of flash EEPROM cells and the relatively large negative voltage that is applied to the control gate insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
Tang et al. 423 describes a method of erasure of a flash EEPROM. A moderately large positive voltage pulse is generated by the source voltage generator VS. Simultaneously, a negative ramp voltage is developed by the gate control voltage generator VG. The drain voltage generator VG will be disconnected from the drain to allow the drain to float and the substrate voltage generator will be set to the ground reference potential as above described. This method will achieve an averaging of the tunneling field during the entire erase cycle.
A variant of the negative gate erase is the positive gate erase discussed in U.S. Pat. No. 5,760,605 (Go). In Go the control gate is brought to a voltage level of approximately +11.0V and the source is brought to the ground reference potential. These biasing conditions allow a net negative potential to be "stored" on the floating gate to establish the "erased" condition. For programming of the flash EEPROM cell the control gate is brought to the ground reference potential, the drain is brought to a voltage of approximately +13.0V and the source is brought to approximately +11.0V. A net positive potential is thus "stored" on the floating gate to establish the "programmed" condition.
Oyama and Hu et al. further discuss techniques for equalization of the threshold voltage V.sub.T after erase or correction of over erase conditions.
U.S. Pat. No. 5,596,528 (Kaya et al.), U.S. Pat. No. 5,491,657 (Haddad et al.), U.S. Pat. No. 5,357,476 (Ku et al.), U.S. Pat. No. 5,598,369 (Chen et al.), U.S. Pat. No. 5,581,502 (Richert et al.), U.S. Pat. No. 5,726,933 (Lee et al. 933) and Hu et al. each describe a form of erasing the flash EEPROM cell 10 conventionally referred to as a Source Erase. To erase the flash EEPROM cell 10 using Source Erase, as shown in FIG. 3a, a relatively high positive voltage (on the order of +10.0V) is generated by the source voltage generator Vs. The control gate voltage generator VG, the P-well voltage generator VPw, and the substrate voltage generator VSub are each set to the ground reference potential. The drain voltage generator VD and the N-well voltage generator VNw are generally disconnected respectively form the drain region 14 and the N-well 47 to allow the drain region 14 and the N-well 47 to be floating. Under these biasing conditions there is similarly a large electric field is developed across the tunneling oxide 36 in the source region 16. This electric field causes the electrons 31 trapped in the floating gate 32 to be extracted to the source region 16 by the Fowler-Nordheim tunneling.
FIG. 3b shows the threshold voltage V.sub.T versus the number of repeated program/erase cycles of the flash EEPROM. As described above, the "hot holes" 38 and the interface traps 40 of FIG. 1 create positive charges that raise the threshold voltage V.sub.T of the flash EEPROM cell. The combination of the decrease 62 in the programmed threshold 60 and the increase 67 of the erased threshold voltage 65 causes the separation of the programmed threshold voltage 60 and the erase threshold voltage 65 to close until the flash EEPROM cell fails. At this time, the flash EEPROM cell will no longer be able to retain the digital data reliably.
U.S. Pat. No. 5,231,602 (Radjy et al.) describes a method of erasing a flash EEPROM cell by controlling the electric field across the tunneling oxide. The drain is connected through a variable resistor to a programming voltage source and a variable voltage source is connected to the source. The variable is voltage source is adjusted between 0 and 5V, while the programming voltage source is set between 5V and 20V. The tunneling current is optimized by adjustment of the variable resistor and the variable voltage.
A third method of erasure of a flash EEPROM cell is described in U.S. Pat. No. 5,521,866 (Akaogi) and is termed a Channel Erase. Channel Erase, as shown in FIG. 4a, has the control gate voltage generator VG set to a relatively large negative voltage (-10.0V) to place the control gate 28 at the relatively large negative voltage. The P-well voltage generator VPw is set to a moderately high voltage (+5.0V) to set the P-well 45 to the moderately high voltage.
The source 16, the drain 14, and the N-well are respectively disconnected from the source voltage generator Vs, the drain voltage generator VD, and the N-well voltage generator VNw to cause the source 16, the drain 14, and the N-well to be floating. The substrate voltage generator VSub is set to the ground reference potential so that the substrate is biased to the ground reference potential.
FIG. 4b illustrates the degradation of the programmed threshold voltage 70 and the erased threshold voltage 75 as the cumulative number of program/erase cycles of the flash EEPROM is increased. In the Channel Erase, the negative charges 31 are extracted across the surface of the floating gate 32 through the tunneling oxide 36 to the P-well 45. Some of these charges will be trapped in the tunneling oxide 36. As the number of program/erase cycles is increase, the programmed threshold voltage 70 begins to decrease 72, while the erased threshold voltage 75 increases modestly 77. This indicates that eventually the difference between the programmed threshold voltage 70 and the erased threshold voltage 75 will eventually decrease until the flash EEPROM cell 10 can no longer retain digital data reliably.
The related patent applications, included herein by reference, illustrate methods to improve the difference in the programmed threshold voltage and the erased threshold voltage by dual phase erasing methods eliminating charges from the floating gate and detrapping the charges from the tunneling oxide of the flash EEPROM cell.